Embodiments of the inventive concept described herein relate to a semiconductor memory device, and more particularly, relate to a semiconductor memory device capable of writing or reading data with a data path configuration and a related method thereof.
The capacity and speed of a semiconductor memory device used in various electronic systems is increasing depending on a demand on high performance of users. For example, dynamic random access memory (DRAM) (a type of volatile memory) stores data in the form of charges that are charged in a cell capacitor.
A cell array of the DRAM may use a row block (or a sub-array) in which memory cells are arranged in rows and columns, as a basic unit. A plurality of bit line sense amplifiers BLSAs connected to corresponding bit lines are interposed between row blocks. Data output from a bit line sense amplifier of a selected column are input to a local sense amplifier LSA through a local data line. The local sense amplifier LSA typically transfers the input data to an even global data line GIOe or an odd global data line GIOo.
However, in a cell array having a bit line sense amplifier of an open bit line structure, there is a limit on the following: the number of row blocks is an odd number. When row blocks placed at an edge of the cell array among row blocks are selected at the same time where and an even number of row blocks exists, data output from these edge row blocks would be transferred to the same global data line (e.g., an even global data line). Thus, if a read operation would be performed on row blocks placed at an edge(s) of a cell array including even-numbered row blocks, data collision occurs at the global data line.
In the case where the even number of row blocks is provided depending on various requirements, the data collision acts as a large limitation on improvement of performance.